1. Field of the Invention
This disclosure relates to a method of fabricating a nonvolatile memory device and more particularly, to a method of fabricating a local SONOS type gate structure and a method of fabricating a nonvolatile memory cell having the gate structure.
2. Description of the Related Art
A nonvolatile memory device is characterized by being able to retain data in a state where supplied electricity is cut-off unlike a volatile memory device. Thus, such a nonvolatile memory device, for example, a flash memory device, has been widely used in file systems, memory cards, portable equipment, or the like.
The nonvolatile memory devices are classified into a stacked gate structure and a SONOS (silicon-oxide-nitride-oxide-silicon) type gate structure depending on the type of its gate structure. The stacked gate structure is typically structured in such a manner that a tunnel oxide layer, a floating gate, an oxide-nitride-oxide (ONO) dielectric layer, and a control gate are sequentially stacked on the channel region of a semiconductor substrate.
Here, hot electron injection is induced to program the nonvolatile memory cell having a stacked gate structure. That is, a high voltage is applied to the control gate and a potential difference between a source region and a drain region is generated. As a result, hot electrons are generated in the channel region near the drain region, and the hot electrons exceed the energy barrier of the tunnel oxide layer so as to be injected into the floating gate. With the injection of the electrons into the floating gate, a threshold voltage is increased. Thus, if a voltage, lower than the increased threshold voltage, is applied to the control gate, an electric current does not flow through the programmed cell. By using these characteristics, the stored information can be read.
Further, the information of a nonvolatile memory cell having the stacked gate structure is erased by removing the electrons in the floating gate by the Fowler-Nordheim (F-N) tunneling mechanism. That is, a high voltage is applied to the source region, 0 V is applied to the control gate and the substrate, and the drain region is floated. As a result, a strong electric field would be generated between the source region and the floating gate so as to induce the F-N tunneling.
On the other hand, the SONOS gate structure is structured in such a manner that a tunnel oxide layer, a trapping dielectric layer, a blocking oxide layer, and a gate electrode are sequentially stacked on the channel region of a semiconductor substrate.
Thus, a nonvolatile memory cell having the SONOS gate structure is programmed typically by inducing hot electron injection, like the memory cell having the stacked gate structure as above. That is, a high voltage is applied to the gate electrode and a potential difference between a source region and a drain region is generated. As a result, hot electrons are generated in the channel region near the drain (or source) region, and the hot electrons exceed the energy barrier of the tunnel oxide layer so as to be injected into the trapping dielectric layer. With the injection of the electrons into the trapping dielectric layer, the threshold voltage is increased. Thus, if a voltage, lower than the increased threshold voltage, is applied to the gate electrode, an electric current does not flow through the programmed cell. By using these characteristics, the stored information can be read.
Here, the electrons inside the trapping dielectric layer can be removed normally by the F-N tunneling mechanism or hot hole injection, etc.
In fact, the SONOS gate structure has many advantages over the stacked gate structure as follows. Firstly, the SONOS gate structure is lower in height than the stacked gate structure. Therefore, the step height difference between the memory cell region and peripheral circuits can be reduced. Secondly, the stacked gate structure requires that the surface of the floating gate be large, but the SONOS gate structure does not require that the surface of the trapping dielectric layer be large. Therefore, the SONOS gate structure is more advantageous than the stacked gate structure to realize the highly-integrated nonvolatile memory devices. Thirdly, as the SONOS gate structure does not include a floating gate, its structure is similar to the gate structure of a typical MOS transistor. Therefore, the above structural characteristic allows for the advantageous use of CMOS technologies, which have been known and acknowledged. Fourthly, as the trapping dielectric layer of the SONOS gate structure is a nonconductive layer, injected electrons cannot move freely. Therefore, the SONOS gate structure has excellent retention characteristics in comparison to the stacked gate structure because it is affected little by pin holes, which may be formed in the tunnel oxide layer.
However, the SONOS gate structure may present some problems associated with an erase operation, i.e., incomplete erase or the like. The problem of incomplete erases, and the verifying method of erase, which may occur in the SONOS gate structure, are disclosed in the U.S. Pat. No. 6,501,681 in the title of “Using a low drain bias during erase verify to ensure complete removal of residual charge in the nitride in SONOS non-volatile memories” to Van Buskirt, et al.
In the meantime, as the trapping dielectric layer is a nonconductive layer, the electrons injected during a program operation do not move freely in the trapping dielectric layer. Therefore, in order to remove the injected electrons, hot holes should be injected through into the same region as the trapping dielectric layer region having the injected electrons distributed there through, or the F-N tunneling should be induced throughout the region. However, the hot hole or the F-N tunneling is induced around a source region or a drain region. Thus, if hot electron injection is induced throughout the broad region of the trapping dielectric layer during the program operation, it is difficult to remove such hot electrons.
Eventually, in order to use the SONOS gate structure, it is necessary to make the electrons injected during the program operation distributed only inside a narrow region of the trapping dielectric layer.